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| MC100EP210S 2.5V 1:5 Dual Differential LVDS Compatible Clock Driver Description The MC100EP210S is a low skew 1-to-5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. Two internal 50 W resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the VTT (VCC - 2.0 V) supply. Designers can take advantage of the EP210S performance to distribute low skew LVDS clocks across the backplane or the board. Features http://onsemi.com MARKING DIAGRAM* MC100 EP210S AWLYYWWG LQFP-32 FA SUFFIX CASE 873A 1 * * * * * * * * * 20 ps Typical Output-to-Output Skew 85 ps Typical Device-to-Device Skew 550 ps Typical Propagation Delay The 100 Series Contains Temperature Compensation Maximum Frequency > 1 GHz Typical Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V Internal 50 W Input Termination Resistors LVDS Input/Output Compatible Pb-Free Packages are Available* 1 32 QFN32 MN SUFFIX CASE 488AM xxx A WL, L YY, Y WW, W G MCxxx EP210S ALYWG = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2006 1 March, 2006 - Rev. 8 Publication Order Number: MC100EP210S/D MC100EP210S Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1 VCC Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 VCC 24 VCC Qa2 Qa2 Qa1 Qa1 Qa0 Qa0 VCC 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 VCC Qb2 Qb2 Qb3 Qb3 Qb4 Qb4 VCC VEE VTA CLKa CLKa VTB CLKb CLKb VEE 1 2 3 4 5 6 7 8 9 CLKa CLKa CLKb VEE VTA VTB CLKb VEE 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 Qa3 23 Qa3 22 Qa4 MC100EP210S 13 12 11 10 9 MC100EP210S 21 Qa4 20 Qb0 19 Qb0 18 Qb1 17 Qb1 VCC Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 VCC Figure 1. 32-Lead QFN Pinout (Top View) Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32-Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION PIN CLKn, CLKn Qn0:4, Qn0:4 VTA VTB VCC VEE EP for QFN-32, only FUNCTION LVDS, LVPECL CLK Inputs* LVDS Outputs 50 W Termination Resistors 50 W Termination Resistors Positive Supply Ground The Exposed Pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat- sinking conduit. The pad is electrically connected to VEE. *Under open or floating conditions with input pins converging to a common termination bias voltage the device is susceptible to auto oscillation. VTA 50 W CLKa CLKa 50 W Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3 Qa4 Qa4 CLKb CLKb 50 W VTB 50 W Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 Qb3 Qb3 Qb4 Qb4 Figure 2. Logic Diagram http://onsemi.com 2 MC100EP210S Table 2. ATTRIBUTES Characteristics ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 2 Value > 2 kV > 100 V > 2 kV Pb-Free Pkg Level 2 Level 1 Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP-32 QFN-32 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 461 Devices Table 3. MAXIMUM RATINGS Symbol VCC VEE VI Iout TA Tstg qJA qJC qJA qJC Tsol Power Supply Power Supply (GND) LVDS, LVPECL Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm 2S2P 32 LQFP 32 LQFP 32 LQFP QFN-32 QFN-32 QFN-32 Parameter Condition 1 VEE = 0 V VCC = 2.5 V VEE = 0 V Continuous Surge VI VCC Condition 2 Rating 6 -6 6 50 100 -40 to +85 -65 to +150 80 55 12 to 17 31 27 12 265 265 Unit V V V mA mA C C C/W C/W C/W C/W C/W C/W C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 3 MC100EP210S Table 4. DC CHARACTERISTICS VCC = 2.5 V, VEE = 0 V (Note 2) -40C Symbol IEE VOH VOL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Internal Termination Resistor Input HIGH Current Input LOW Current CLK CLK -150 -150 1250 800 1.2 Min Typ 150 1400 950 Max 200 1550 1100 2.5 1250 800 1.2 Min 25C Typ 150 1400 950 Max 200 1550 1100 2.5 1250 800 1.2 Min 85C Typ 150 1400 950 Max 200 1550 1100 2.5 Unit mA mV mV V RT IIH IIL 43 57 150 150 150 43 50 57 150 43 57 150 W mA mA -150 -150 150 150 -150 -150 150 150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. 3. All loading with 100 W across LVDS differential outputs. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 5. AC CHARACTERISTICS VCC = 2.375 to 2.625 V, VEE = 0 V (Note 5) -40C Symbol fmaxLVDS/ LVPECL tPLH tPHL tskew Characteristic Maximum Frequency (See Figure 2. Fmax/JITTER) Propagation Delay Within-Device Skew (Note 6) Device-to-Device Skew (Note 7) Duty Cycle Skew (Note 8) RMS Random Clock Jitter Minimum Input Swing Output Rise/Fall Time (20%-80%) 150 50 425 Min Typ >1 525 20 85 80 0.2 800 130 625 25 160 100 <1 1200 200 150 75 450 Max Min 25C Typ >1 550 20 85 80 0.2 800 150 650 25 160 100 <1 1200 225 150 80 475 Max Min 85C Typ >1 575 20 85 80 0.2 800 160 675 35 160 100 <1 1200 230 Max Unit GHz ps ps tJITTER VPP tr/tf ps mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. 6. 7. 8. Measured with 400 mV source, 50% duty cycle clock source. All loading with 100 W across differential outputs. Skew is measured between outputs under identical transitions of similar paths through a device. Device-to-Device skew for identical transitions at identical VCC levels. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. http://onsemi.com 4 MC100EP210S 450 400 350 VOUTpp (mV) 300 250 200 150 100 50 0 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz) Simulated Figure 2. Fmax Q Driver Device Q 100 W D Receiver Device D Figure 3. Typical Termination for Output Driver and Device Evaluation ORDERING INFORMATION Device MC100EP210SFA MC100EP210SFAG MC100EP210SFAR2 MC100EP210SFAR2G MC100EP210SMNG MC100EP210SMNR4G Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) QFN-32 (Pb-Free) Shipping 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 72 Units / Tray 1000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MC100EP210S PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A-02 ISSUE B -T-, -U-, -Z- AE P V AE 8 17 A 32 4X 25 A1 0.20 (0.008) AB T-U Z 1 -T- B B1 DETAIL Y -U- V1 DETAIL Y BASE METAL N -Z- 9 S1 S 8X 4X F D M_ R J G -AB- SEATING PLANE DETAIL AD CE SECTION AE-AE -AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF K Q_ GAUGE PLANE DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X http://onsemi.com 6 0.20 (0.008) 0.20 (0.008) AC T-U Z EE EE EE 9 M AC T-U Z MC100EP210S PACKAGE DIMENSIONS QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O A B NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500 D 2X 2X 0.15 C 0.15 C 0.10 C 32 X 0.08 C L 32 X 8 1 32 32 X b 0.10 C A B 25 0.05 C BOTTOM VIEW 32 X ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. EE EE TOP VIEW SIDE VIEW D2 9 16 17 PIN ONE LOCATION E (A3) A A1 C EXPOSED PAD SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L K 32 X SOLDERING FOOTPRINT* 5.30 E2 3.20 24 32 X 0.63 e 3.20 5.30 0.28 28 X 0.50 PITCH *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MC100EP210S/D |
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